/**************************************
@ filename    : uart_test_env.v
@ author      : yyrwkk
@ create time : 2025/04/17 23:46:06
@ version     : v1.0.0
**************************************/
`include "uart_test_env.vh"
module uart_test_env (
    input         i_clk            ,
    input         i_rst_n          ,
   
    input         i_rx             ,
    output        o_tx             ,
   
    input         i_wr_valid       ,
    input  [7:0]  i_wr_data        ,
    output        o_wr_ready       ,
   
    output        o_rd_valid       ,
    output [7:0]  o_rd_data        ,
    input         i_rd_ready    
);

wire          uart_rx_valid;
wire [7:0]    uart_rx_data ;
wire          uart_rx_ready; 

wire          uart_tx_valid;
wire [7:0]    uart_tx_data ;
wire          uart_tx_ready; 

uart_rx #(
    .CFG_BAUD_DIV    (`UART_BAUD_DIV   ),
    .CFG_TARGET_BITS (`UART_TARGET_BITS),
    .CFG_PARITY_EN   (`UART_PARITY_EN  ),
    .CFG_PARITY_SEL  (`UART_PARITY_SEL )
)uart_rx_inst(
    .clk_i        (i_clk         ),
    .rstn_i       (i_rst_n       ),
    
    .rx_i         (i_rx          ),

    .busy_o       (              ),
    .err_o        (              ),

    .rx_data_o    (uart_rx_data  ),
    .rx_valid_o   (uart_rx_valid ),
    .rx_ready_i   (uart_rx_ready )
);

stream_fifo  # (
    .DATA_WIDTH  (8               ), 
    .ADDR_WIDTH  (`FIFO_ADDR_WIDTH)
)stream_fifo_inst_in(
    .wr_valid     (uart_rx_valid  ),
    .wr_din       (uart_rx_data   ),
    .wr_ready     (uart_rx_ready  ),

    .rd_valid     (o_rd_valid     ),                   
    .rd_dout      (o_rd_data      ),
    .rd_ready     (i_rd_ready     ),

    .clk          (i_clk          ),
    .rst_n        (i_rst_n        )  
);

uart_tx  #(
    .CFG_BAUD_DIV    (`UART_BAUD_DIV   ),
    .CFG_TARGET_BITS (`UART_TARGET_BITS),
    .CFG_PARITY_EN   (`UART_PARITY_EN  ),
    .CFG_PARITY_SEL  (`UART_PARITY_SEL ),
    .CFG_STOP_BITS   (`UART_STOP_BITS  )
)uart_tx_inst(
    .clk_i        (i_clk  ),
    .rstn_i       (i_rst_n),

    .tx_o         (o_tx         ),
    .busy_o       (             ),

    .tx_data_i    (uart_tx_data ),
    .tx_valid_i   (uart_tx_valid),
    .tx_ready_o   (uart_tx_ready)
);

stream_fifo  # (
    .DATA_WIDTH  (8               ), 
    .ADDR_WIDTH  (`FIFO_ADDR_WIDTH)
)stream_fifo_inst_out(
    .wr_valid     (i_wr_valid     ),
    .wr_din       (i_wr_data      ),
    .wr_ready     (o_wr_ready     ),
 
    .rd_valid     (uart_tx_valid  ),                   
    .rd_dout      (uart_tx_data   ),
    .rd_ready     (uart_tx_ready  ),

    .clk          (i_clk          ),
    .rst_n        (i_rst_n        )  
);

endmodule 